1. Field of the Invention
The present invention relates to a memory system having a plurality of direct memory access (DMA) channels and an integrated management method for the plurality of DMA channels. More particularly, the present invention relates to a memory system which has a plurality of DMA channels and allows access to a memory through a plurality of channels to maximize data transmission efficiency by integratedly controlling the corresponding channels, and an integrated management method for the plurality of DMA channels.
The present invention was supported by the IT R&D program of MKE. [2008-S-006-04, Component Module for Ubiquitous Terminal].
2. Discussion of Related Art
General memory controllers array data toward a system memory or data from the system memory as fast as a memory device allows. Since the memory controller can process data as fast as the memory device allows, this does not limit a bandwidth. Meanwhile, one method of increasing a bandwidth is to increase a rate of a memory data bus connecting the memory controller to the memory devices. However, the memory devices cannot catch up with increases in data bandwidth of the memory controller and the memory data buses.
Meanwhile, specific memory controllers have a plurality of channels to raise memory accessibility of a plurality of processors or peripheral devices. However, although the memory controllers have the plurality of channels, they cannot increase bandwidths. These controllers only provide an advantage of allocating the entire data transmission bandwidth that can be provided by the memory to a device of the destination via the plurality of channels. In other words, the memory controller having the plurality of channels can provide several channels but cannot increase a memory bandwidth because it actually allows a single memory access. However, due to the plurality of channels, the memory controller can previously access a spare channel to prepare a memory access operation, and equally divide the bandwidth when the plurality of channels have equal priorities to access the memory.
In the memory controllers having the plurality of channels, like a memory controller having one channel, a free-charging time is essential for next data transmission after data is transmitted using one channel. However, when data is simultaneously transmitted using the plurality of channels provided by the memory controller, the memory controller can previously prepare next data transmission, and thus transmission performance of a memory can be enhanced. For example, a dynamic random access memory (DRAM) needs a plurality of clock periods to activate a row and free-charge a memory bank. Thus, a waiting time corresponding to the plurality of clock periods is needed. Depending on the length of a burst to be read or written, the waiting time may correspond to more clock periods than those used for pure data transmission. However, when next data transmission is prepared during the reading or writing burst, the waiting time of the memory is included in the pure data transmission time, and data transmission efficiency can be enhanced. Such an effect may be obtained by the memory controller having the plurality of channels.
Accordingly, a DMA channel controller and an integrated channel management method for effectively using a multi-channel memory controller are required to obtain such an effect.